关键词: 系统级芯片, 测试调度, 知识产权核, 测试访问机制, 遗传算法, 差分进化

Abstract: To reduce testing time of electronic applications using System on Chip (SoC) design, an optimal bus assignment scheme based on genetic algorithm was presented for SoC test scheduling. A genetic algorithm model for optimal test scheduling was constructed. To make the solution process more stable and the results nearer to global optimal solution, differential evolution, elitism approach and self-adaptive mutation were introduced to the traditional genetic algorithm. The approach provided more optimal test time clock cycles, comparable to the Integer Linear Programming(ILP) formulation of similar problems, the comparison results indicated that this approach was more appropriate to test the large-scale SoC.

Key words: system on chip, test scheduling, intellectual property cores, test access mechanism, genetic algorithm, differential evolution