关键词: 片上网络, 三维拓扑, 延时, 功耗, 性能评估

Abstract: The power consumption and delay performance of regular Three-Dimensional (3D) topology and define 3D topology were analyzed and compared. Besides, the proposal for topology structure of network on chip design was given. According to current focus of 3D topology design, 3D-Mesh, 3D-Torus, custom topology with long-links and network partitioning techniques were selected as analysis objects. By analyzing four topological structures and generation method, the delay and power consumption evaluation models were proposed. The values of delay and power consumption were simulated and calculated under different scale and injection rates. Experimental result showed that topology with long-links was applied to the strict situation to delay, and network partitioning techniques outperformed other topologies in power consumption. The standard topology had better tradeoff in design complexity, delay and power consumption.

Key words: network on chip, three dimensional topology, delay, power consummation, performance evaluation