Computer Integrated Manufacturing System ›› 2024, Vol. 30 ›› Issue (4): 1273-1285.DOI: 10.13196/j.cims.2021.0698

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Adaptive variable step size scanning and matching algorithm based on local chip distribution feature identification

WU Tao1,ZHOU Yi1,HUANG Zhixiong1,YE Weilin1,WU Fupei1,LI Bin2   

  1. 1.Department of Mechatronics Engineering,Shantou University
    2.School of Mechanical Science,Huazhong University of Science and Technology
  • Online:2024-04-30 Published:2024-05-09
  • Supported by:
    Project supported by the Guangdong Provincial Natural Science Foundation,China(No.2018A030307049,2021A1515010661),and the Guangdong Provincial Science and Technology Plan Project,China (No.STKJ2021027).

局域芯片分布特征辨识及自适应变步长扫描与匹配

吴涛1,周意1,黄智雄1,叶玮琳1,吴福培1,李斌2   

  1. 1.汕头大学智能制造技术教育部重点实验室
    2.华中科技大学机械科学与工程学院
  • 基金资助:
    广东省自然科学基金资助项目(2018A030307049,2021A1515010661);广东省科技计划资助项目(STKJ2021027)。

Abstract: To solve problems of missing scanning and matching error in LED die testing and sorting,an adaptive variable step size scanning method was proposed to analyze regional die distribution characteristics by using the continuity and retention of the local deformation of adhesive membrane,and to make available step size adjustment.At the prober,a characterization and description method based on 8-neighborhood location model was proposed,and an adaptive variable step size adjustment strategy was established.At the sorter,a traversal matching method was put forward to make plan for reasonable scanning area and path with normalized map and physical address map produced in prober.The experimental results showed that such algorithm could limit the scanning redundancy ratio to less than 4%,obtain the missed scanning ratio less than 0.5% and improve the scanning performance by about 23% than that of traditional redundancy-based scanning method.Because only searching for qualified dies,the matching rate of nearly 100% could be achieved,and the efficiency and anti-interference ability of the algorithm could be significantly improved.

Key words: wafer bin map, logic view normalization, active traversal, position relationship, index match

摘要: 为解决LED芯片检测与分选中的漏扫、匹配错误等关键问题,提出自适应变步长扫描方法。该方法对当前局域分布特性进行分析,利用晶圆片局部形变的连续性与保持性对邻近区域芯片分布进行预测,实施步长调整。在检测端,提出基于8邻域位置模型的区域芯片分布特征表征与描述方法,确立自适应步长调整策略,建立物理地址映射视图以及归一化逻辑视图。在分选端,利用已知物理地址映射图和归一化逻辑视图,对扫描区域、步长与路径进行规划,在遍历芯片的同时,实现芯片匹配。实测表明,相比冗余方法,该方法能够以低于4%的冗余率,实现漏扫率低于0.5%,提升扫描效率近23%。由于只针对有意义的芯片进行查找,可实现接近100%的匹配率,显著改善了算法效率和抗干扰能力。

关键词: 晶圆片映射视图, 逻辑归一化, 主动遍历, 位置关系, 索引匹配

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