[1]VIKRAM K N, VASUDENVAN V. Hardware-software co-simulation of bus-based reconfigurable systems[J]. Microprocecessors and Microsystems,2005,29(4):133-144.
[2]DIMITROULAKOS G, GALANIS M D, GOUTIS C E. Design space exploration of an optimized compiler approach for a generic reconfigurable array architecture[J]. The Journal of Supercomputing,2007,40(2):127-157.