计算机集成制造系统 ›› 2021, Vol. 27 ›› Issue (7): 2005-2015.DOI: 10.13196/j.cims.2021.07.015

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活塞杆抛光表面微细缺陷的快速筛查技术

姜庆胜,李研彪,计时鸣+   

  1. 浙江工业大学机械工程学院
  • 出版日期:2021-07-31 发布日期:2021-07-31
  • 基金资助:
    国家自然科学基金面上资助项目(51575494);浙江省自然科学基金重点资助项目(LZ14E050001)。

Rapid screening technology for micro-fine defects polished surface of piston rod

  • Online:2021-07-31 Published:2021-07-31
  • Supported by:
    Project supported by the National Natural Science Foundation,China(No.51575494),and the Zhejiang Provincial Natural Science Foundation,China(No.LZ14E050001).

摘要: 为了使汽车减振器活塞杆表面品质实现自动化快速检测,满足批量生产过程中的实时在线全检需求,提出一种基于计算统一设备架构(CUDA)的活塞杆抛光表面微细缺陷的快速筛查技术。该技术使用线扫描成像方法在活塞杆圆柱面高光反射情况下清晰获取4 096×16 384的高分辨率图像,然后采用改进的二维间隔冲击阵列(TDIIA)卷积滤噪算法实现快速滤波和筛查,较串行计算速度提升了52.4倍;通过串并混编,与并行规约求和算法结合,使缺陷筛查计算总体时间较串行方法耗时节省了67.4%。另外,该方法为面向精密检测的高分辨率图像的巨大数据量在线实时处理提供了一种参考方法。

关键词: 机器视觉, 表面缺陷, 并行计算, 计算统一设备架构

Abstract: To realize the automatic and rapid detection of the surface quality of automobile shock absorber piston rod and to meet the real-time online inspection requirements in the mass production process,a rapid screening technology of the micro-fine defects of the polished surface of the piston rod based on Compute Unified Device Architecture (CUDA) was proposed.In this technique,a high-resolution image of 4096x16384 was clearly obtained using a line scan imaging method in the case of piston rod high-reflection of cylindrical surface,and then a modified Two Dimensional Interval Impulse Array (TDIIA) convolution filter was used.The algorithm realized fast filtering and screening,which was 52.4 times faster than the serial computing speed.By mixing program of serial and parallel algorithm,and combining with the parallel reduction summation algorithm,the overall time of defect screening calculation was 67.4% less than the serial method.In addition,the technology provided a reference method for online real-time processing of large data volumes oriented to high-resolution images of precision detection.

Key words: machine vision, surface defect, parallel computation, compute unified device architecture

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